This invention relates to electronic circuits, and more particularly, to amplifier circuits useful in low power supply voltage applications.
Amplifier circuits are used in a variety of electronic systems for increasing the voltage, current, or power of a signal. FIG. 1 shows one example of an amplifier 100 configured to receive an input voltage, Vin, and provide an amplified voltage, Vout. Amplifier 100 includes a positive input terminal 101 (“V+”), a negative input terminal 102 (“V−”), an output terminal 103 (“Vout”), a positive supply terminal 104, and a negative supply terminal 105. Input voltage, Vin, is received on terminal 101, and the amplified voltage, Vout, is provided on terminal 103. Amplifier 100 includes feedback resistors 106 (“R1”) and 107 (“R2”), which are connected in a “closed loop” to provide negative feedback. The output voltage, Vout, of amplifier 100 is related to the inputs according to the following well-known equation:Vo=G(V+−V−),where “G” is the “open loop” gain of amplifier 100. If the open loop gain “G” of amplifier 100 is sufficiently large, then the “closed loop” gain of the present configuration is approximately given by the following:Vo/Vin=(1+R2/R1)
In some applications, an amplifier must maintain its input-output relationship with a high level of accuracy across a substantial portion of the output voltage range. However, in many actual implementations, the accuracy of an amplifier can be impaired by non-linearities in the open loop gain. To solve this problem, it is possible to utilize a closed loop configuration, such as the one illustrated in FIG. 1, with an amplifier that has a high open loop gain to achieve a closed loop system with high accuracy. Accordingly, it is desirable to have an amplifier circuit with a high open loop gain.
One trend in integrated circuit technology that has created challenges for amplifier circuit designers is the continuing reduction in the power supply voltages used in electronic systems. As power supply voltages are decreased, an amplifier's open loop gain can become constrained by the maximum and minimum voltages allowable on the amplifier's internal nodes. The difference between a maximum and minimum allowable voltage on a given node is referred to herein as “headroom.” As the headroom of an amplifier's internal nodes is constrained by reductions in supply voltage, the gain of the amplifier may also have to be reduced so that intermediate signals do not exceed allowable levels.
FIGS. 2A and 2B show common amplifier circuits known in the art in order to illustrate the headroom limitations discussed above. Amplifier 200 shown in FIG. 2A is one example of a cascaded common source stage and common gate stage referred to as a “cascode” stage. The term cascode stage refers a variety of circuit structures that include one or more cascode transistors. In the present example, a simple two transistor structure is shown. In amplifier 200, NMOS transistor 211 is the input device and NMOS transistor 212 is the cascode device (i.e., the cascode transistor). Amplifier 200 also includes a current source 230. Transistor 211 receives an input signal Vin and generates a current proportional to the input voltage. Cascode transistor 212 is biased by a fixed voltage Vb1, and routes the current to the output while simultaneously increasing the output impedance of the circuit. The approximate gain of amplifier 200 is given by the following equation:Vout/Vin≈gm1ro2(1+gm2ro2)Where gm1 and gm2 are transconductances and ro1 and ro2 are output impedances of transistors 211 and 212, respectively.
Cascode circuits are useful because they provide very high gain. However, cascode circuits achieve higher gains at the expense of headroom. The loss in headroom may be illustrated by first noting that both transistors 211 and 212 should remain in saturation to achieve optimum gain performance. Therefore, the minimum output voltage can be expressed as follows:Vout≧VGS1−VTH1+VGS2−VTH2Where VGS1 and VGS2 are the gate to source voltages and VTH1 and VTH2 are the threshold voltages of transistors 211 and 212, respectively.
FIG. 2B shows a cascode circuit 250 including a cascode current source which limits the maximum allowable output voltage. In cascode circuit 250, the ideal current source has been replaced with a cascode current source comprising PMOS transistors 213 and 214 biased by voltages Vb2 and Vb3, respectively. A cascode current source is useful because the high output impedance associated with such structures yields a current source closer to an ideal current source. However, for optimum operation the maximum output voltage is limited as follows:Vout≦VS−|VGS3−VTH3|−|VGS4−VTH4|Where VGS3 and VGS4 are the gate to source voltages and VTH3 and VTH4 are the threshold voltages of transistors 213 and 214, respectively.
Accordingly, known cascode circuits are advantageous because they provide large gain. On the other hand, known cascode circuits are disadvantageous for low power supply applications because they have limited headroom. This limited headroom can impact the ability of the circuit to amplify currents or voltages at the output or at intermediate nodes. More particularly, at low power supply voltages, headroom limitations constrain the ability of cascode stages to drive inputs of transistors in an output stage across wide voltage ranges. These limitations result in output stages that cannot provide accurate output voltages across wide voltage ranges. What is needed is an amplifier circuit that provides high gain that can operate effectively at low power supply voltage levels.